1. Field of the Invention
The present invention relates to yield enhancement schemes and techniques. More specifically, the present invention relates to soft-error detection and mitigation of redundant columns and rows within a semiconductor memory device.
2. Description of Related Art
Large-scale semiconductor memory devices have memory cells that are typically subject to hard and soft errors. A hard error results from a defect in the memory by which a cell becomes fixed in one logical state or the other. A soft error occurs when a bit of stored data changes to an incorrect value. Soft errors are data errors that may result from radiation, such as alpha particles, or from other effects. Conventional digital error correction codes have been employed to detect errors, making correctable errors detectable in semiconductor memory devices. One method of decreasing the number of rejected semiconductor memory devices has been to replace defective memory cells with spare, redundant cells that have been incorporated within the device itself. Replacement has been achieved in the prior art through the substitution of a complete row for the defective row, or a complete column for the corresponding defective column.
Generally, a memory array contains a plurality of column decoders for enabling access to columns in the array, each column decoder being associated with a respective group of columns and arranged to access one of the columns.
If a memory cell is defective, yield enhancement schemes may be employed to implement row redundancy or to bypass a defective column. A memory cell is selected by externally applying row address signals and column address signals. A row decoder responds to the input row address to select memory cells of one row for a read or write operation. A column decoder selects one column according to the input column address and further selects one memory cell out of the one row of memory cells selected according to the row address. When a memory cell is found to be defective, the memory may be reconfigured to replace the row affected or, conversely, all the cells of the affected column with a spare column.
Typically, RAMs have a set number of original rows or word lines and a plurality of spare word lines. Reconfiguration may be performed by implementing a fuse element associated with each spare word line in a main memory array. When a memory cell is determined to be defective, the fuses for the corresponding word line address are blown to decouple the main address decoder from the row incorporating the defective memory cell. The address of the defective row is programmed into a spare address decoder that selects a spare row of memory cells in response to subsequent read or write access operations to the defective address in the main memory array. Alternatively, one may reconfigure a memory to implement spare column replacement. Blowing fuses and letting the values of the blown fuse circuitry steer the column redundancy is one means of accomplishing this. For example, some systems reroute the defective column's column enable line to the spare column. Address reordering schemes are well known and have been used often in the art.
In U.S. Pat. No. 6,249,467 issued to Pereira, et al., entitled “ROW REDUNDANCY IN A CONTENT ADDRESSABLE MEMORY,” a content addressable memory (CAM) device allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. Each spare row is used to functionally replace a defective row in the same CAM block or any other CAM block by programming the address of the defective row into the corresponding spare address decoder.
In U.S. Pat. No. 5,963,489 issued to Kirihata, et al., entitled “METHOD AND APPARATUS FOR REDUNDANCY WORD LINE REPLACEMENT IN A REPAIRABLE SEMICONDUCTOR MEMORY DEVICE,” a row redundancy replacement arrangement is provided wherein a word line selector circuit and redundancy controlled logic and address inputs allow the redundant true (complement) word lines to replace the normal true (complement) word lines when making a repair.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a means to enhance reliability when a soft error upset has occurred in redundancy registers.
It is another object of the present invention to provide a soft error yield enhancement scheme to registers that contain replacement information for redundant rows and single bit slices.
A further object of the invention is to provide a circuit design to minimize soft error upset in memory devices.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.